■ FEATURES
• Power supply voltage of 2.7 to 3.6 V
• High performance
    85 ns maximum access time
• Operating Temperature
    −25 to +85 °C
• Package 61-ball FBGA, 56-pin TSOP(I)

1. FLASH MEMORY
• Simultaneous Read/Write operations (dual bank)
    Miltiple devices available with different bank sizes
    Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
    Zero latency between read and write operations
    Read-while-erase
    Read-while-program
• Minimum 100,000 write/erase cycles
• Sector erase architecture
    Eight 4 K words and thirty one 32 K words.
    Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
    MB84VD2108X : Top sector
    MB84VD2109X : Bottom sector
• Embedded EraseTM* Algorithms
    Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
    Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready-Busy output (RY/BY)
    Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
    When addresses remain stable, automatically switch themselves to low power mode.
• Low VCCf write inhibit ≤ 2.5 V
• Hidden ROM (Hi-ROM) region
    64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
    Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
    At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status
    (MB84VD2108X : SA37, SA38 MB84VD2109X : SA0, SA1)
    At VIH, allows removal of boot sector protection
    At VACC, program time will reduse by 40%.
• Erase Suspend/Resume
    Suspends the erase operation to allow a read in another sector within the same device
• Please refer to “MBM29DL16XTD/BD” data sheet in detailed function

2. SRAM
• Power dissipation
    Operating: 50 mA max.
    Standby: 7 µA max.
• Power down features using CE1s and CE2s
• Data retention supply voltage : 1.5 V to 3.6 V
• CE1s and CE2s Chip Select
• Byte data control : LBs (DQ0 to DQ7) , UBs (DQ8 to DQ15)