■ DESCRIPTION

The MB86830 series is a SPARClite *1 series of RISC architecture processors, providing high performance for a variety of embedded applications. Conforming to the SPARC *2 architecture, the MB86830 series is upward code compatible with the conventional products in the SPARClite family. When running at 100 MHz, the MB86830 series provides performance of 121 VAX-MIPS.

■ FEATURES

• IU (integer unit)

   Maximum operating frequency : 120 MHz

   SPARC architecture V8E conforming

   With 32-bits general register :136 / register window : 8

• Instruction cash

   The entry lock function is supported

• Data cache

   No cash controlling function supported

   The entry lock function is supported

• BIU (bus interface unit)

   Purifetchi baffa :1

   Write buffer :4

   The burst mode is supported

   Programmable chip selection function :6

   Programmable weight state control :6

   For 8/16/32-bits bus

   Automatic insertion function of idling cycle after ROM region is accessed

   For burst mode ROM

• With internal clock multiplication circuit

• Sleep mode (low power consumption mode) supported

• With DRAM controller (except on the MB86836)

• With interrupt request controller (IRC)

• On-chip general-purpose 16-bit timer (MB86836 only):1 channel (equivalent to the MB86942)

• Support for the JTAG test port (MB86836 only)