GENERAL DESCRIPTION
The 128Mb (x32) DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728- bits. It is internally configured as a quadbank DRAM.

FEATURES
• VDD = +2.5V ±0.125V, VDDQ = +2.5V ±0.125V
• Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture
• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
• Reduced and matched output drive options
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable burst lengths: 2, 4, 8, or full page
• 32ms, 4,096-cycle auto refresh
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 2.5V I/O (SSTL_2 compatible)
• DQS per byte on the FBGA package
• 1.8V VDDQ option for FBGA package
• tRAS lockout