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SLG46170 Scheda tecnica(PDF) 12 Page - Dialog Semiconductor

Il numero della parte SLG46170
Spiegazioni elettronici  Personal Computers and Servers
PDF  87 Pages
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Produttore elettronici  DIALOG [Dialog Semiconductor]
Homepage  http://www.dialog-semiconductor.com/
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SLG46170 Scheda tecnica(HTML) 12 Page - Dialog Semiconductor

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SLG46170
5.5 IDD Estimator
5.6 Timing Estimator
5.7 Typical Counter/Delay Offset Measurements
Table 1. Typical Current estimated for each macrocell.
Symbol
Parameter
Note
VDD = 1.8 V VDD = 3.3V VDD = 5.0V
Unit
I
Current
Chip Quiescent
0.5
0.8
1.0
A
OSC 25 kHz, predivide = 1
3.2
5.1
7.3
A
OSC 25 kHz, predivide = 8
3.0
4.4
6.0
A
OSC 2 MHz, predivide = 1
38.5
78.2
136.2
A
OSC 2 MHz, predivide = 8
18.3
25.7
35.5
A
Table 2. Typical Delay estimated for each macrocell.
Symbol Parameter
Note
VDD = 1.8 V
VDD = 3.3V
VDD = 5.0V
Unit
rising falling rising falling rising falling
tpd
Delay
Digital input to PP 1X
42
45
17
19
12
13
ns
tpd
Delay
Digital Input with Schmitt Trigger to PP
1X
42
43
16
17
18
12
ns
tpd
Delay
Low Voltage Digital input to PP 1X
45
428
17
177
12
120
ns
tpd
Delay
Digital input to PMOS
42
-
17
-
12
-
ns
tpd
Delay
Digital input to NMOS
-
80
-
27
-
18
ns
tpd
Delay
Output enable from pin, OE Hi-Z to 1
53
-
21
-
15
-
ns
tpd
Delay
Output enable from pin, OE Hi-Z to 0
50
-
20
-
14
-
ns
tpd
Delay
LUT2bit(LATCH)
34
33
14
13
10
9
ns
tpd
Delay
LATCH(LUT2bit)
30
34
14
13
10
9
ns
tpd
Delay
LUT3bit(LATCH)
38
37
18
15
13
10
ns
tpd
Delay
LATCH+nRESET(LUT3bit)
45
42
21
17
15
12
ns
tpd
Delay
LUT4bit
28
33
14
13
10
9
ns
tpd
Delay
LUT2bt
19
26
10
10
7
7
ns
tpd
Delay
LUT3bit
28
34
14
13
10
9
ns
tpd
Delay
CNT/DLY
40
38
18
15
13
11
ns
tpd
Delay
P_DLY1C
380
377
166
163
123
120
ns
tpd
Delay
P_DLY2C
720
718
314
312
233
231
ns
tpd
Delay
P_DLY3C
1061
1060
462
460
343
341
ns
tpd
Delay
P_DLY4C
1396
1400
609
609
451
451
ns
tpd
Delay
Filter
200
200
78
78
53
53
ns
tpd
Delay
ACMP (5mV across inputs)
3000
3000
2000
2000
2000
2000
ns
tw
width
I/O with 1X push pull (min transmitted)
20
20
20
20
20
20
ns
tw
width
filter (min transmitted)
150
150
55
55
35
35
ns
Table 3. Typical Counter/Delay Offset Measurements.
Parameter
RC OSC
Freq
RC OSC Power
VDD = 1.8 V VDD = 3.3V VDD = 5.0V
Unit
offset
25kHz
auto
19
14
12
s
offset
2MHz
auto
7
4
4
s
frequency settling time
25kHz
auto
19
14
12
s



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