EM6605 datasheet(9/43 Pages) NSC

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EM6605

Table 8.Prescaler control register - PRESC

Bit

Name

Reset

R/W

Description

MTim

R/W

Timer/Counter Interrupt Mask

PRST

R/W

Prescaler reset

PSF1

R/W

Prescaler Interrupt select 1

PSF0

R/W

Prescaler Interrupt select 0

5. Watchdog timer

If for any reason the CPU crashes, then the watchdog timer can detect this situation and output a system

reset signal. This function can be used to detect program overrun. For normal operation the watchdog

timer must be reset periodically by software at least once every three seconds (*f1) (CLK = 32kHz) or a

system reset signal is generated to CPU and periphery. The watchdog is active during STANDBY. The

watchdog reset function can be deactivated by setting the NoWD bit to 1 in the Option register.

In worst case because of prescaler reset function WD time-out can come down to 2 seconds.

The watchdog timer is reset by writing 1 to the WDRST bit. Writing 0 to WDRST has no effect.

The watchdog timer also operates in STANDBY mode. It is therefore necessary to reset it if this mode

continues for more than three seconds (*f1). One method of doing this is to reset it with the prescaler ck[1]

interrupt (1Hz *f1 such, that the watchdog is reset every second).

Table 9.Watchdog register - WD

Bit

Name

Reset

R/W

Description

WDRST

R/W

Watchdog timer reset

Slmask

R/W

SLEEP mask bit

WD1

WD Timer data ck[1]/4 (1/4Hz *f1)

WD0

WD Timer data ck[1]/2 (1/2 Hz *f1)

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