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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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CS8952 Scheda tecnica(PDF) 60 Page - Cirrus Logic |
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CS8952 Scheda tecnica(HTML) 60 Page - Cirrus Logic |
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60 / 82 page  CS8952 60 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 5 CIM Status Read Only 0 When clear, this bit indicates that a stable link con- nection has been detected. When an unstable link is detected and the Carrier Integrity Monitor Disable bit in the PCS Sub-Layer Configuration Register (address 17h) is clear, this bit is set and latched. It will remain set until this register is read. 4:0 PHY Address Field Read/Write Reset to the val- ues on the PHYAD[4:0] pins. The value on pins PHYAD[4:0] are latched into this field at power-up or reset. These bits define the PHY address used by the management layer to address the PHY. The external logic must know this address in order to select this particular CS8952’s registers individually via the MDIO and MDC pins. BIT NAME TYPE RESET DESCRIPTION |
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