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ADUCM310 Scheda tecnica(PDF) 13 Page - Analog Devices |
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ADUCM310 Scheda tecnica(HTML) 13 Page - Analog Devices |
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13 / 28 page  ADuCM310 Data Sheet Rev. B Page 12 of 27 4 The internal reference calibration and trimming are performed when the processor operates in normal mode with CD = 0, when ADC is enabled and converting, when IDACs are all on, and when VDACs are on. VREF accuracy can vary under other operating conditions. 5 Measured using the following box method: ( ) ( ) ( ) 6 1 2.5 × − × − Minimum e Temperatur Maximum e Temperatur e Temperatur Any at Minimum V e Temperatur Any at Maximum V REF REF 6 VDAC linearity specifications are calculated with following ranges: VDAC0 and VDAC1 = +150 mV to +2.699 V VDAC2 and VDAC3: −150 mV to −4.22 V VDAC4 and VDAC5: +150 mV to +2.98 V VDAC6: +150 mV to +4.747 V VDAC7: +150 mV to +4.297 V 7 Analog Devices, Inc., production IDAC full-scale trimming conditions include PVDD_IDACx pin voltage = 0.7 V, all IDACs on. 8 The long-term stability specifications is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period. 9 For all VDAC specifications for VDAC0, VDAC1, VDAC4, and VDAC5, DACxCON[10:9] = 11. 10 VDACx minimum and maximum limits apply to the internal reference only (DACxCON[1:0] = 00b). AVDDx supply valid only with typical specifications. 11 The average current from the GPIO pins must not exceed 3 mA per pin. See Figure 22. TIMING SPECIFICATIONS I2C Timing Table 2. I2C Timing in Standard Mode (100 kHz) Slave Parameter Description Min Typ Max Unit tL SCLx low pulse width 4.7 µs tH SCLx high pulse width 4.0 ns tSHD Start condition hold time 4.0 µs tDSU Data setup time 250 ns tDHD Data hold time (SDAx held internally for 300 ns after falling edge of SCLx) 0 3.45 µs tRSU Setup time for repeated start 4.7 µs tPSU Stop condition setup time 4.0 µs tBUF Bus free time between a stop condition and a start condition 4.7 µs tR Rise time for both SCLx and SDAx 1 µs tF Fall time for both SCLx and SDAx 15 300 ns tVD;DAT Data valid time 3.45 µs tVD;ACK Data valid acknowledge time 3.45 µs Table 3. I2C Timing in Fast Mode (400 kHz) Slave Parameter Description Min Typ Max Unit tL SCLx low pulse width 1.3 µs tH SCLx high pulse width 0.6 ns tSHD Start condition hold time 0.3 µs tDSU Data setup time 100 ns tDHD Data hold time (SDAx held internally for 300 ns after falling edge of SCLx) 0 µs tRSU Setup time for repeated start 0.6 µs tPSU Stop condition setup time 0. 3 µs tBUF Bus free time between a stop condition and a start condition 1.3 µs tR Rise time for both SCLx and SDAx 20 300 ns tF Fall time for both SCLx and SDAx 15 300 ns tVD;DAT Data valid time 0.9 µs tVD;ACK Data valid acknowledge time 0.9 µs |
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