ATPL00B datasheet(46/152 Pages) ATMEL

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Atmel ATPL00B [datasheet]

43028A-ATPL - 9/12

Table 4-13. P3, P4, P5 ports Alternate Functions

Alternate Function

P3.0

RxD (serial port 0 input)

P3.1

TxD (serial port 0 output)

P3.2

INT0 (external interrupt 0)

P3.3

INT1 (external interrupt 1)

P3.4

T0 (timer 0 external input)

P3.5

T1 (timer 1 external input)

P3.6

WR(external data memory write strobe)

P3.7

RD (external data memory read strobe)

P4.0

RxD (serial port 2 input)

P4.1

TxD (serial port 2 output)

P4.2

SS1 (SPI1 slave select input)

P4.3

SPICLK1 (SPI1 clock input/output)

P4.4

MOSI1 (SPI1 master out / slave in data)

P4.5

MISO1 (SPI1 master in / slave out data

P4.6

T2 (timer 2 input/output)

P4.7

T2EX (timer 2 external input)

P5.0

SS (SPI0 slave select input)

P5.1

SPICLK (SPI0 clock input/output)

P5.2

MOSI (SPI0 master output / slave input data)

P5.3

MISO (SPI0 master input / slave output data)

P5.4

RxD (serial port 1 input)

P5.5

TxD (serial port 1 output)

Note:

To use an Alternate Function the corresponding bit (or bits) in the SFR must contain a 1.

4.7.1

I/O Configurations

Figure 4-13 and Figure 4-14 show a functional diagram of bit register and I/O buffer in each of the four ports. The level

of the port pin is placed on the internal bus and instructions can read the port pin value or the SFR register value.

If a bit in a register with AOF (Alternate Output Function) contains a 1, then the output level is controlled by the signal

labeled “Alternate Output function”.

Figure 4-13. Pins with AOF structure

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