| Motore di ricerca datesheet componenti elettronici |
|
ATPL230A Scheda tecnica(PDF) 10 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
ATPL230A Scheda tecnica(HTML) 10 Page - ATMEL Corporation |
|
10 / 122 page ![]() ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 10 5.3 Zero-crossing detection 5.3.1 Overview Zero Crossing Detector block works predicting future zero crossings of the Mains signal in function of its past zero crossings. To achieve this, the system embeds a configurable Input Signal Management (ISM) block and a PLL, both of which manage Zero Crossing Detector Input Signal to calculate Zero Crossing Output Flag. The zero-cross detection of waves of 50 Hz and 60 Hz with ±10% of error is supported. The PLL block interprets its input signal such a way that it indicates a zero cross in the middle of a positive pulse. It is important to note that depending on the external circuit implementing the Zero Crossing Detector Input Signal this interpretation is not always correct. Thus, for some cases it is required to transform the Input Signal in a signal where the middle of a positive pulse corresponds to a truly zero cross. This transformation is implemented through the Input Signal Management (ISM) block, configured by MODE_INV and MODE_REP fields in ZC_CONFIG register. Zero Crossing Detector Input Signal (VZ CROSS) must fulfil some requirements. The first requirement is that VZ CROSS signal must be a pulse train with a duty cycle being >60% or <40% (polarity is configurable). In addition, if we have to detect ascent or descent zero-crossing, the Zero Crossing Detector Input Signal period must be equal than the period of the wave we need to obtain zero-crossing. Ascent and descent Zero Crossing Detection are configured by setting MODE_MUX and MODE_ASC fields in ZC_CONFIG register. Figure 5-3. Typical circuit, using a bidirectional optocoupler and a Schmitt trigger The input signal “VZ CROSS” (wider line) generated by this circuit for Zero Cross Detection of the wave “L”-“N” (finer line) is plotted in next figure. The digital signal at output of Input Signal Management (ISM) is plotted in Figure 5-4. Figure 5-4. Digital signal (dashed line) at output of Input Signal Management (ISM) internal block Mains Signal ZC signal provided to VZ CROSS |
|
Link URL |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | Collegamento alla scheda tecnica | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |