SN74ALS166

PARALLEL-LOAD 8-BIT SHIFT REGISTER

SDAS156D – APRIL 1982 – REVISED AUGUST 2000

5

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

LOAD CIRCUIT FOR OUTPUT UNDER TEST

TEST TABLE FOR SYNCHRONOUS INPUTS

SH/LD

H0 V

4.5 V

QH at tn + 1

QH at tn + 1

VOLTAGE WAVEFORMS

RL = 500 Ω

CL = 50 pF

(see Note A)

From Output

Under Test

Test

Point

3.5 V

0.3 V

3.5 V

0.3 V

3.5

0.3 V

VOH

VOL

tw(clear)

1.3 V

1.3 V

tn + 1 (see Note D)

tn

tn

tn + 1

tw(CLK)

tsu

th

CLR

(see Note C)

CLK

(see Note E)

Data Input

(see Test Table)

Output QH

tPHL

tPLH

tPHL

Serial input

DATA INPUT

FOR TEST

OUTPUT TESTED

(see Note B)

1.3 V

1.3 V

1.3 V

tsu

th

1.3 V

1.3 V

1.3 V

1.3 V

NOTES: A. CL includes probe and jig capacitance.

B. Propagation delay times (tPLH and tPHL) are measured at tn+1. Proper shifting of data is verified at tn+8 with a functional test.

C. A clear pulse is applied prior to each test.

D. tn = bit time before clocking transition, tn+1 = bit time after one clocking transition, and tn+8 = bit time after eight clocking transitions.

E. The clock pulse has the following characteristics: tw(clock) ≤ 20 ns and PRR = 1 MHz. The clear pulse has the following

characteristics: tw(clear) ≤ 20 ns.

F. All pulse generators have the following characteristics: ZO ≈ 50 Ω; tr = tf = 2 ns. Duty cycle = 50% when testing fmax.

1.3 V

Figure 1. Load Circuit and Voltage Waveforms