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VSC8061FI Scheda tecnica(PDF) 5 Page - Vitesse Semiconductor Corporation

Il numero della parte VSC8061FI
Spiegazioni elettronici  2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset
PDF  20 Pages
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Produttore elettronici  VITESSE [Vitesse Semiconductor Corporation]
Homepage  http://www.vitesse.com
Logo VITESSE - Vitesse Semiconductor Corporation

VSC8061FI Scheda tecnica(HTML) 5 Page - Vitesse Semiconductor Corporation

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VITESSE
SEMICONDUCTOR CORPORATION
G52069-0, Rev 4.3
Page 5
05/11/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Data Sheet
VSC8061/VSC8062
Multiplexer/Demultiplexer Chipset
2.5Gb/s 16-Bit
VSC8062 Demultiplexer AC Characteristics (Over recommended operating range)
Figure 6: VSC8062 Timing Diagram
Table 2: VSC8062 AC Characteristics
NOTES: (1) If tCLK changes, all remaining parameters change as indicated by the equations.
(2) tSU and tH are setup and hold times of the serial data input register.
(3) At tCLK = 400ps.
Parameter
Description
Min
Typ
Max
Units
Conditions
tCLK
Clock period(1)
400
ps
tD
BYTE CLK16 period (tCLK x 16)
6.4
ns
tDSU
CLK16 falling edge output to valid data
1.0
3.0
ns
tDH
Phase Margin =
Serial data phase timing margin with respect to
high-speed clock(2)
180(3)
degrees
tCLK
High-speed differential clock input
CLK (CLKN)
High-speed serial data input
DI (DIN)
Parallel data clock output
CLK16
D0
D1
D15
tD
tBD
tD
1
tSU tH
+
tCLK
-------------------

 360°
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