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SL28PCIe10ALCT Scheda tecnica(PDF) 8 Page - Silicon Laboratories |
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SL28PCIe10ALCT Scheda tecnica(HTML) 8 Page - Silicon Laboratories |
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8 / 16 page ![]() SL28PCIe10 .......................................Document #: Rev 1.1 Page 8 of 16 Byte 13: Control Register 13 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 10: Control Register 10 (continued) Bit @Pup Name Description Byte 11: Control Register 11 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 1 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 12: Byte Count Bit @Pup Name Description 7 0 BC7 Byte count register for block read operation. The default value for Byte count is 15. In order to read beyond Byte 15, the user should change the byte count limit.to or beyond the byte that is desired to be read. 60 BC6 50 BC5 40 BC4 31 BC3 21 BC2 11 BC1 01 BC0 Bit @Pup Name Description 7 1 REF_Bit2 Drive Strength Control - Bit[2:0], Note: See Byte 6 Bit 5 for REF Slew Rate Bit 1 and Byte 6 Bit 3 for 27MHz Slew Rate Bit 1 Normal mode default ‘101’ Wireless Friendly Mode default to ‘111’ 61 REF_Bit0 5 1 27MHz_NSS_Bit2 4 1 27MHz_NSS_Bit0 3 1 Prog_SE_Bit2 2 1 Prog_SE_Bit0 1 0 RESERVED RESERVED 0 0 Wireless Friendly mode Wireless Friendly Mode 0 = Disabled, Default all single-ended clocks slew rate config bits to ‘101’ 1 = Enabled, Default all single-ended clocks slew rate config bits to ‘111’ |
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