5812-DS00-R datasheet(51/84 Pages) BOARDCOM

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Advance Data Sheet

BCM5812

3/11/03

B roa dcom Co rpo rat ion

Document

5812-DS01-405-R

Endian Considerations

Page 43

The byte order that is seen at a device on the PCI bus is the same in both cases. When used with a big endian host

processor, this is sometimes referred to as a match byte lanes policy.

Unfortunately, this policy produces the wrong result for non-byte stream data, including fields built by the host processor as

16-bit lengths, 32-bit addresses, or 32-bit BigNum elements. These appear in the BCM5812 MCR, command context, and

fragment chain entry structures. Ordinarily, host software would have to byte swap such fields in order to undo the effect of

the byte swap.

The BCM5812 provides two software enabled endian control flags for adjusting the byte order to match the host processor

system configuration and minimize or eliminate the need for byte swapping in software. Table 14 on page 44 describes

these flags. The default setting at reset is for a little endian host processor on a typical PCI bus configuration.

Figure 38: Typical Little Endian Processor PCI Bus Configuration

7...0

15..8

23..16

31.24

63..56 55.48 47.40 39.32

7...0

15..8

23..16

31.24

PCI Bus W ord 0

PCI Bus W ord 1

111

110

101

100

011

010

001

000

Byte Address

Bit Number

W ord in host memory

7...0

15..8

23..16

31.24

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