AD9480 datasheet(16/28 Pages) AD

16 / 28 page

AD9480

Rev. 0 | Page 16 of 28

SFDR

SNR

SINAD

SAMPLE CLOCK (MHz)

150

200

100

250

300

Figure 26. SNR, SINAD, SFDR vs. Sample Clock Frequency,

AIN = 70 MHz

−1 dBFS

ANALOG INPUT DRIVE LEVEL (dBFS)

–70

–60

–40

–50

–30

–20

–10

SFDRdBFS

SFDRdBc

65dB

REF LINE

Figure 27. SFDR vs. AIN Input Level; AIN = 70 MHz at 250 MSPS

MHz

–20

–10

–50

–40

–30

–70

–60

–90

–80

060

100

120

F1, F2 = –7dBFS

2F2-F1 = –71.1dBc

2F1-F2 = –68dBc

Figure 28. Two-Tone Intermodulation Distortion

(69.3 MHz and 70.3 MHz; fS = 250 MSPS)

ENCODE (MSPS)

180

160

100

120

140

100

200

250

150

300

IAVDD

IDRVDD

Figure 29. IAVDD and IDRVDD vs. Clock Rate, CLOAD = 5 pF

AIN = 70 MHz @ –1 dBFS

DCS OFF

DCS ON

CLOCK POSITIVE DUTY CYCLE (%)

Figure 30. SNR, SINAD vs. Clock Pulse Width High,

AIN = 70 MHz @ –1 dBFS, 250 MSPS, DCS On/Off

EXTERNAL VREF VOLTAGE (V)

50.0

47.5

45.0

42.5

40.0

0.5

1.1

0.9

0.7

1.5

1.3

1.7

1.9

SNR

SFDR

SINAD

Figure 31. SNR, SINAD, and SFDR vs. VREF in External Reference Mode,

AIN = 70 MHz @ –1 dBFS, 250 MSPS

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