PIC12CE673-10SLASHJM datasheet(34/129 Pages) MICROCHIP

34 / 129 page

PIC12C67X

DS30561B-page 34

6.1.5

ACKNOWLEDGE

The EEPROM, when addressed, will generate an

acknowledge after the reception of each byte. The pro-

cessor must generate an extra clock pulse which is

associated with this acknowledge bit.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. The processor must signal an end of data to

the EEPROM by not generating an acknowledge bit on

the last byte that has been clocked out of the EEPROM.

In this case, the EEPROM must leave the data line

HIGH to enable the processor to generate the STOP

condition (Figure 6-4).

FIGURE 6-1:

BLOCK DIAGRAM OF GPIO6 (SDA LINE)

FIGURE 6-2:

BLOCK DIAGRAM OF GPIO7 (SCL LINE)

Note:

Acknowledge bits are not generated if an

internal programming cycle is in progress.

Reset

Data Bus

Write

Output Latch

To EEPROM SDA

Schmitt Trigger

ltchpin

Input Latch

Read

VDD

Pad

GPIO

Data Bus

Write

To EEPROM SCL

ltchpin

Read

VDD

Pad

Schmitt Trigger

GPIO

Output Latch

PIC12CE673-10/JM Scheda tecnica(PDF) 34 Page - Microchip Technology

PIC12CE673-10/JM Scheda tecnica(HTML) 34 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL