AM29SL160C datasheet(13/52 Pages) AMD

13 / 52 page

November 1, 2004

Am29SL160C

RESET# pin is driven low for at least a period of tRP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all read/

write commands for the duration of the RESET# pulse.

The device also resets the internal state machine to

reading array data. The operation that was interrupted

should be reinitiated once the device is ready to accept

another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS ± 0.2 V, the device

draws CMOS standby current (ICC4). If RESET# is held

at VIL but not within VSS ± 0.2 V, the standby current is

greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase oper-

ation, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The

system can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of tREADY (not during Embedded Algo-

rithms). The system can read data tRH after the

RESET# pin returns to VIH.

Refer to “AC Characteristics” on page 37 for RESET#

parameters and to “RESET# Timings” on page 38 for

the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is

disabled. The output pins are placed in the high imped-

ance state.

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