CLC417 datasheet(4/8 Pages) NSC

4 / 8 page

http://www.national.com

CLC417 Typical Performance Characteristics (Vcc = ±5V, Av = +2, R

L = 100Ω

Ω; unless specified)

CLC417 OPERATION

Description

The CLC417 is a dual current feedback buffer with the

following features:

Gains of +1, -1, and 2 are achievable without

external resistors

Differential gain and phase errors of 0.01%

and 0.03° into a 150

Ω load

Low, 3.9mA, supply current per amplifier

The convenient 8-pin package and internal resistors

make common applications, like that seen on the front

page, easily feasible in a limited amount of space. The

professional video quality differential gain and phase

errors and low power capabilities of the CLC417 make

this product a good choice for video applications.

If gains other than +1, -1, or +2V/V are required, then the

CLC416 can be used.

The CLC416 is a dual current

feedback amplifier with near identical performance, and

allows for external feedback and gain resistors.

Closed Loop Gain Selection

Gains of +1, +2, and -1V/V can be achieved by both of

the CLC417’s amplifiers. Implement the gain selection

by connecting the inverting (-IN) and non-inverting (+IN)

pins as described in the table below.

The gain accuracy of the CLC417 is excellent and

stable over temperature. The internal feedback and gain

setting resistors, Rf and Rg, are diffused silicon resistors.

Rf and Rg have a process variation of ±20% and a

temperature coefficient of ~ 2000ppm/°C. Although the

absolute values of Rf and Rg change with processing and

temperature, their ratio (Rf/Rg) remains constant. If an

external resistor is used in series with Rg, gain accuracy

over temperature will be impacted by temperature coeffi-

cient differences between internal and external resistors.

Non-Inverting Unity Gain Considerations

Gains of +1V/V are obtained by removing all resistive

and capacitive connections between the inverting

pins and ground on the CLC417 amplifiers. Too much

capacitive coupling between the inverting pin and ground

may cause stability problems. Minimize this capacitive

coupling by removing the ground plane near the

input and output pins. The response labeled

open in

Figure 1 is the result of the inverting pin left open and all

capacitive coupling removed. A flatter response can be

obtained

inserting

resistor

between

the

inverting and non-inverting pins as shown in Figure 2.

The two remaining plots in Figure 1 illustrate a 300

Ω

resistor and a short connected between pins 2 and 3 of

the CLC417.

Figure 1: Frequency Response vs.

Unity Gain Configuration

Figure 2: Optional Unity Gain Configuration

PSRR and CMRR

10k

100k

Frequency (Hz)

10M

100M

PSRR

CMRR

Typical DC Errors vs. Temperature

Temperature (

°C)

-50

100

IBN

-1

-2

-3

IBI

VIO

Power Derating Curves

Ambient Temperature (

°C)

0.8

1.0

0.6

100

120 140

160 180

0.4

0.2

AJE

AJP

Frequency (MHz)

100

Short

Open

R = 300

Ω

250

Ω

250

Ω

250

Ω

250

Ω

SMA

Input1

Rin

Ω

SMA

Output1

Rout

Ω

NOTE: The same technique can also

be applied to Channel B. Bypass

capacitors not shown.

Gain

Input Connections

+IN

-IN

-1V/V

ground

input signal

+1V/V

input signal

NC (open)

+2V/V

input signal

ground

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