LP1110-00

Oct.-2017

www.lowpowersemi.com

Page 2 of 8

Preliminary Datasheet LP1110

Functional Pin Description

Package Type

Pin Configurations

DFN8

BST

PWM

EN

VCC

DRVH

DRVL

PGND

SWN

(TOP View)

1

2

3

4

5

6

7

8

Pin

Name

Description

1

BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and

SW pins holds this bootstrap voltage for the high-side MOSFET as it is switched. The

recommended capacitor valueis between 100nF and 1.0μF. An external diode is

required with the LP1110.

2

PWM

Logic-Level Input. This pin has primary control of the drive outputs.

3

EN

Active high output enable. When low, normal operation is disabled forcing DRVH and

DRVL low.

4

VCC

Input Supply. A 1.0μF ceramic capacitor should be connected from this pin to PGND.

5

DRVL

Output drive for the lower MOSFET.

6

PGND

Power Ground. Should be closely connected to the source of the lower MOSFET.

7

SWN

Switch Node. Connect to the source of the upper MOSFET.

8

DRVH

Output drive for the upper MOSFET.