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dc2425af

DEMO MANUAL DC2425A

SIGNAL CONNECTIONS

J1 FPGA Program: Factory use only.

J2 JTAG: Factory use only.

J3 AIN+ Input: In the single-ended configuration, this is

the signal input. For differential operation, this serves as

the positive signal input.

J4 AIN– Input: This input is used only for differential

operation. It serves as the negative signal input.

J5 CLK: This input has a 50Ω termination resistor, and is

intended to be driven by a low jitter 10dBm sine or square

wave. To achieve the full AC performance of this part,

the clock jitter should be kept under 2ps. This input is

capacitively coupled so that the input clock can be either

0V to 2.5V or ±1.25V. This eliminates the need for level

shifting. To run at the maximum conversion rate, apply

the frequency specified in the Table 1.

JP1 VCCIO: Use this jumper to select the VCCIO supply

voltage. The default setting is 2.5V. The 1.8V setting

selects a 1.8V supply voltage.

JP2 VDD: Use this jumper to select the VDD supply volt-

age. The default setting is 5V. The 3.3V setting selects a

3.3V supply voltage.

JP3: Use this jumper to select the reference source for

the LTC2311. The default setting is DRIVE REFOUT. This

setting uses the voltage applied to Pin 3 of the LTC2311

as the reference voltage. The EXT setting will accept a

voltage applied to E11 as the reference voltage. If no volt-

age is applied to E11, the LTC2311 will use it's internal

reference, which is 4.096V.

JP4 +IN Coupling: Use this jumper to select AC- or DC-

coupling of the signal applied to J3. The default setting

is DC. At very low input frequencies, using AC-coupling

may degrade the distortion performance.

JP5 Mode: Use this jumper to select the signal input mode

for the LTC2311. The default setting is DIFF. The DIFF

setting accepts a single-ended signal from J3 but applies

it as a differential signal to the LTC2311. The BIP setting

accepts a single-ended signal from J3 and applies it as

a single-ended bipolar signal to the LTC2311. The UNI

setting also accepts a single-ended signal from J3, and

applies it as a unipolar signal to the LTC2311. See Drive

Options section fro more details.

JP6 –IN Coupling: Use this jumper to select AC- or DC-

coupling of the signal applied to J4. The default setting

is DC. At very low input frequencies, using AC-coupling

may degrade the distortion performance.

JP7 CM: Use this jumper to set the DC bias point for the

signal applied to J3 when JP4 (+IN coupling) is in the

AC position. The default setting is 4.096V which sets the

common mode voltage at 2.048V. The EXT setting allows

the use of an externally applied common mode voltage

applied at E12 (EXT_CM1).

JP8 Data Out: Use this jumper to select the data output

format from the LTC2311. The default setting is CMOS.

The output data will not be valid if the jumper is moved

to the LVDS position unless the following changes have

been made:

Install 100Ω 0402 resistors at R26, 75, 76, 99

Reprogram the CPLD through J1 using the program-

ming file LTC2311.pof found at:

http://www.linear.com/demo/DC2425A

Move JP8 to the LVDS position.

JP9 EEPROM: Factory use only.

JP10 OSC: Use this jumper to enable the onboard encode

clock source. The default setting is OFF. The ON setting

energizes this source. Refer to the DC2425A schematic for

additional passive elements required to use the onboard

source.

harDware setup