LTC2604IGN datasheet(12/16 Pages) LINER

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LTC2604/LTC2614/LTC2624

2604f

OPERATIO

other hand, all four DACs are powered down, then the main

bias generation circuit block has been automatically shut

down in addition to the individual DAC amplifiers and

reference inputs. In this case, the power up delay time is

µs (for VCC = 5V) or 30µs (for VCC = 3V).

Voltage Outputs

Each of the four rail-to-rail amplifiers contained in these

parts has guaranteed load regulation when sourcing or

sinking up to 15mA at 5V (7.5mA at 3V).

Load regulation is a measure of the amplifier’s ability to

maintain the rated voltage accuracy over a wide range of

load conditions. The measured change in output voltage

per milliampere of forced load current change is ex-

pressed in LSB/mA.

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change in

units from LSB/mA to Ohms. The amplifiers’ DC output

impedance is 0.025

Ω when driving a load well away from

the rails.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by the

Ω typical channel resistance of the output devices; e.g.,

when sinking 1mA, the minimum output voltage = 30

Ω •

1mA = 25mV. See the graph Headroom at Rails vs Output

Current in the Typical Performance Characteristics

section.

The amplifiers are stable driving capacitive loads of up to

1000pF.

Board Layout

The excellent load regulation and DC crosstalk perfor-

mance of these devices is achieved in part by keeping

“signal” and “power” grounds separate.

The PC board should have separate areas for the analog

and digital sections of the circuit. This keeps digital signals

away from sensitive analog signals and facilitates the use

of separate digital and analog ground planes which have

minimal capacitive and resistive interaction with each

other.

Digital and analog ground planes should be joined at only

one point, establishing a system star ground as close to

the device’s ground pin as possible. Ideally, the analog

ground plane should be located on the component side of

the board, and should be allowed to run under the part to

shield it from noise. Analog ground should be a continu-

ous and uninterrupted plane, except for necessary lead

pads and vias, with signal traces on another layer.

The GND pin functions as a return path for power supply

currents in the device and should be connected to analog

ground. Resistance from the GND pin to system star

ground should be as low as possible. When a zero scale

DAC output voltage of zero is desired, the REFLO pin

(pin 2) should be connected to system star ground.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is

limited to voltages within the supply range.

Since the analog outputs of the device cannot go below

ground, they may limit for the lowest codes as shown in

Figure 3b. Similarly, limiting can occur near full scale

when the REF pins are tied to VCC. If REF x = VCC and the

DAC full-scale error (FSE) is positive, the output for the

highest codes limits at VCC as shown in Figure 3c. No full-

scale limiting can occur if REF x is less than VCC – FSE.

Offset and linearity are defined and tested over the region

of the DAC transfer function where no output limiting can

occur.

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