PCI4451 datasheet(72/216 Pages) TI

72 / 216 page

4–4

4.5

Status Register

The status register provides device information to the host system. Bits in this register may be read normally. A bit

in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit

functions adhere to the definitions in the PCI Bus Specification, as seen in the bit descriptions. PCI bus status is shown

through each function. See Table 4–3 for a complete description of the register contents.

Bit

Name

Status

Type

R/W

Default

Status

Type:

Read-only, Read/Write

Offset:

06h (Functions 0, 1)

Default:

0210h

Table 4–3. Status Register Description

BIT

SIGNAL

TYPE

FUNCTION

PAR_ERR

R/W

Detected parity error. This bit is set when a parity error is detected, either address or data parity errors. Write

a 1 to clear this bit.

SYS_ERR

R/W

Signaled system error. This bit is set when SERR is enabled and the PCI4451 signaled a system error to

the host. Write a 1 to clear this bit.

MABORT

R/W

Received master abort. This bit is set when a cycle initiated by the PCI4451 on the PCI bus has been

terminated by a master abort. Write a 1 to clear this bit.

TABT_REC

R/W

Received target abort. This bit is set when a cycle initiated by the PCI4451 on the PCI bus was terminated

by a target abort. Write a 1 to clear this bit.

TABT_SIG

R/W

Signaled target abort. This bit is set by the PCI4451 when it terminates a transaction on the PCI bus with

a target abort. Write a 1 to clear this bit.

10–9

PCI_SPEED

DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired to 01b indicating that the

PCI4451 asserts this signal at a medium speed on nonconfiguration cycle accesses.

DATAPAR

R/W

Data parity error detected. Write a 1 to clear this bit.

0 = The conditions for setting this bit have not been met.

1 = A data parity error occurred and the following conditions were met:

a. PERR was asserted by any PCI device including the PCI4451.

b. The PCI4451 was the bus master during the data parity error.

c. The parity error response bit is set in the command register.

FBB_CAP

Fast back-to-back capable. The PCI4451 cannot accept fast back-to-back transactions; thus, this bit is

hardwired to 0.

UDF

UDF supported. The PCI4451 does not support the user definable features; therefore, this bit is hardwired

to 0.

66MHZ

66-MHz capable. The PCI4451 operates at a maximum PCLK frequency of 33 MHz; therefore, this bit is

hardwired to 0.

CAPLIST

Capabilities list. This bit returns 1 when read. This bit indicates that capabilities in addition to standard PCI

capabilities are implemented. The linked list of PCI power management capabilities is implemented in this

function.

3–0

RSVD

These bits return 0s when read.

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