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TLE9255WLC Scheda tecnica(PDF) 83 Page - Infineon Technologies AG |
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TLE9255WLC Scheda tecnica(HTML) 83 Page - Infineon Technologies AG |
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83 / 100 page ![]() Data Sheet 83 Rev. 1.02 2018-02-02 TLE9255W Electrical Characteristics Table 16 CAN FD 4.75 V < VCC <5.25 V; 3.0V< VIO < 5.5 V; 5.5V < VBAT < 40V; RL =60 Ω; -40 °C < TJ < 150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. CAN FD Characteristics Received recessive bit width at 2 MBit/s tBit(RxD)_2M 400 500 550 ns CL = 100 pF, CRxD =15 pF, tBit = 500 ns,; (see Figure 49); P_10.4.36 Received recessive bit width at 5 MBit/s tBit(RxD)_5M 120 200 220 ns CL = 100 pF, CRxD =15 pF, tBit = 200 ns; (see Figure 49); P_10.4.37 Transmitted recessive bit width at 2 MBit/s tBit(Bus)_2M 435 500 530 ns CL = 100 pF, CRxD =15 pF, tBit = 500 ns; (see Figure 49); P_10.4.38 Transmitted recessive bit width at 5 MBit/s tBit(Bus)_5M 155 200 210 ns CL = 100 pF, CRxD =15 pF, tBit = 200 ns; (see Figure 49); P_10.4.39 Receiver timing symmetry at 2MBit/s ∆tRec_2M = tBit(RxD)_2M - tBit(Bus)_2M ∆tRec_2M -65 – 40 ns CL = 100 pF, CRxD =15 pF, tBit = 500 ns, (see Figure 49); P_10.4.40 Receiver timing symmetry at 5MBit/s ∆tRec_5M = tBit(RxD)_5M - tBit(Bus)_5M ∆tRec_5M -45 – 15 ns CL = 100 pF, CRxD =15 pF, tBit = 200 ns, (see Figure 49); P_10.4.41 |
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