| Motore di ricerca datesheet componenti elettronici |
|
MP6528 Scheda tecnica(PDF) 9 Page - Monolithic Power Systems |
|
|
|||||||||||||||||||||||||||||
MP6528 Scheda tecnica(HTML) 9 Page - Monolithic Power Systems |
|
9 / 17 page ![]() MP6528 – 5V TO 60V, H-BRIDGE GATE DRIVER MP6528 Rev. 1.03 www.MonolithicPower.com 9 6/20/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description 1 VIN Input supply voltage. Bypass to ground with a ceramic capacitor. Additional bulk capacitance may be required. See Applications Information section. 2 CPA Charge pump capacitor. Connect a ceramic capacitor between these pins. See Applications Information section. 3 CPB 4 VREG Gate drive supply output. Connect a ceramic capacitor to ground. See Applications Information section. 5 BSTA Bootstrap phase A. Connect a ceramic capacitor to SHA. See Applications Information section. 6 SHA High-side source connection phase A. 7 GHA High-side gate drive phase A. 8 GLA Low-side gate drive phase A. 9, 10, 11, 12 NC No connection. Leave these pins open. 13 BSTB Bootstrap phase B. Connect a ceramic capacitor to SHB. See Applications Information section. 14 SHB High-side source connection phase B. 15 GHB High-side gate drive phase B. 16 GLB Low-side gate drive phase B. 17 LSS Low-side source connection. 18 PWMB PWM input pin for phase B. High drives phase B high; low drives phase B low. Internal pulldown. 19 GND Ground. 20 PWMA PWM input pin for phase A. High drives phase A high; low drives phase A low. Internal pulldown. 21 ENB Enable pin for phase B. Active high enables the gate driver for phase B; low disables the gate driver for phase B. Internal pulldown.. 22 GND Ground. 23 ENA Enable pin for phase A. Active high enables the gate driver for phase A; low disables the gate driver for phase A. Internal pulldown. 24 nFAULT Fault indication. Open-drain output. nFAULT is logic low when in a fault condition. 25 nSLEEP Sleep mode input. Logic low to enter low-power sleep mode; high to enable. Internal pulldown. 26 OCREF Over-current protection reference voltage input. 27 DT Dead time setting. Connect a resistor to ground to set the dead time. See Applications Information section. 28 GND Ground. |
|
|
Link URL |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | Collegamento alla scheda tecnica | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |