TPS720

SBVS100E – JUNE 2008 – REVISED SEPTEMBER 2015

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6.2 ESD Ratings

VALUE

UNIT

±2000

Charged-device model (CDM), per JEDEC specification JESD22-

Electrostatic discharge

±500

V

Machine model (MM)

±100

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

Input voltage (steady-state)

1.1

(1)

V

Bias voltage

5.5

V

Output voltage

0.9

3.6

V

Peak output current

0

350

mA

Input capacitance

1

µF

Bias capacitance

0.1

µF

(3)

Output capacitance

2.2

µF

(1)

Whichever is less

(2)

Whichever is greater

(3)

Maximum ESR should be less than 250 m

Ω.

6.4 Thermal Information

TPS720

DRV (SON)

YZU (WSCP)

UNIT

6 PINS

5 PINS

Junction-to-ambient thermal resistance

66.5

144.9

°C/W

Junction-to-case (top) thermal resistance

86.2

1.1

°C/W

Junction-to-board thermal resistance

36.1

27.5

°C/W

Junction-to-top characterization parameter

1.7

4.1

°C/W

Junction-to-board characterization parameter

36.6

27.4

°C/W

Junction-to-case (bottom) thermal resistance

7.4

N/A

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

4

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