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80C86 Scheda tecnica(PDF) 21 Page - Renesas Technology Corp |
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80C86 Scheda tecnica(HTML) 21 Page - Renesas Technology Corp |
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21 / 38 page ![]() 80C86 FN2957 Rev 4.00 Page 21 of 38 August 19, 2015 FIGURE 7B. BUS TIMING - MINIMUM MODE SYSTEM NOTE: Two INTA cycles run back-to-back. The 80C86 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown for the second INTA cycle. Waveforms (Continued) t4 t3 t2 t1 TW TDVCL TCLDX1 (7) TWHDX TCVCTX TCHCTV (30) TCLAV TCLAZ TCHCTV (31) TCVCTX TCVCTV (17) (26) (27) (29) TCVCTV DATA OUT AD15-AD0 INVALID ADDRESS CLK (82C84A OUTPUT) WRITE CYCLE (RD, INTA, DT/R = VOH) AD15-AD0 DEN WR INTA CYCLE (SEE NOTE) (RD, WR = VOH BHE = VOL) AD15-AD0 DT/R INTA DEN AD15-AD0 SOFTWARE HALT - DEN, RD, WR, INTA = VOH DT/R = INDETERMINATE SOFTWARE HALT (29) TCVCTV POINTER TCL2CL1 (5) tW TCLAV TCLDV TCLAX (18) TCLDX2 (29) (28) TWLWH (38) (29) TCVCTV (19) TCVCTX (31) (6) (30) (31) (17) TCH1CH2 (4) |
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