ISL54221 datasheet(4/13 Pages) RENESAS

4 / 13 page

ISL54221

FN6820 Rev 0.00

Page 4 of 13

December 16, 2008

Skew, (tSKEWOUT - tSKEWIN)VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, RL = 45,

CL = 10pF,tR = tF = 720ps at 480Mbps,

(Duty Cycle = 50%) (see Figure 6)

Rise/Fall Degradation (Propagation

Delay), tPD

VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, RL = 45,

CL = 10pFsee Figure 6)

250

Crosstalk

VDD = 3.3V, RL = 50, f = 240MHz (see Figure 5)

-36

OFF-Isolation

VDD = 3.3V, OE = 3.3V, RL = 50, f = 240MHz

-32

-3dB Bandwidth

Signal = 0dBm, 0.2Vdc offset, RL = 50

742

MHz

OFF Capacitance, CHSxOFF

f = 1MHz, VDD = 3.3V, SEL = 0V, OE = 3.3V, VHSD1x or

VHSD2x = VDx = 0V (see Figure 4)

2.8

COM ON Capacitance, CDX(ON)

f = 1MHz, VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V,

VHSD1x or VHSD2x = VDx = 0V (see Figure 4)

7.4

POWER SUPPLY CHARACTERISTICS

Power Supply Range, VDD

Full

2.7

5.5

Positive Supply Current, IDD

VDD = 5.5V, SEL = 0V or VDD, OE = 0V or VDD

0.009

0.03

µA

Full

µA

Positive Supply Current, IDD

VDD = 4.3V, SEL = 2.6V, OE = 0V or 2.6V

0.159

0.6

µA

Full

1.6

µA

Positive Supply Current, IDD

VDD = 3.6V, SEL = 1.4V, OE = 0V or 1.4V

6.6

µA

Full

µA

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, VSELL, VOEL

VDD = 2.7V to 3.6V

Full

0.5

Input Voltage High, VSELH, VOEH

VDD = 2.7V to 3.6V

Full

1.4

Input Voltage Low, VSELL, VOEL

VDD = 4.3V to 5.5V

Full

0.8

Input Voltage High, VSELH, VOEH

VDD = 4.3V to 5.5V

Full

2.0

Input Current, ISELL, IOEL

VDD = 5.5V, SEL = 0V, OE = 0V

Full

3.3

Input Current, ISELH

VDD = 5.5V, SEL = 5.5V

Full

-3.6

Input Current, IOEH

VDD = 5.5V, OE = 5.5V

Full

-8.2

NOTES:

4. VLOGIC = Input voltage to perform proper function.

5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

7. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range

8. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON

value, between HSD2+ and HSD2- or between HSD1+ and HSD1-.

9. Limits established by characterization and are not production tested.

Electrical Specifications - 2.7V to 5.5V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V,

VOEH = 1.4V, VOEL = 0.5V, (Note 4), Unless Otherwise Specified (Continued)

PARAMETER

TEST CONDITIONS

TEMP

(°C)

MIN

(Notes 5, 6)

TYP

MAX

(Notes 5, 6) UNITS

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