EM6580WS11 datasheet(10/55 Pages) EMMICRO

10 / 55 page

EM6580

03/07, rev. J

www.emmicroelectronic.com

4.4 Sleep Counter Reset

To profit the most from Low Power Sleep Mode and still supervise the circuit surrounding, one can enable the

Sleep Counter Reset which only runs in Sleep mode and periodically wakes up the EM6580. Four (4) different

Wake-Up periods are possible as seen in table below.

Control bits SleepCntDis which is set to default ‘0’by POR enables the Sleep Counter when the circuit goes

into Sleep mode. The SCRsel1, SCRsel0 bits that are used to determine Wake-Up period are in the

RegSleepCR register. To disable the Sleep Counter in Sleep mode SleepCntDis must be set to ‘1’.

Table 4.4.2 Register RegSleepCR

Bit

Name

Reset

R/W

Description

NoPullPA[4]

0 por

R/W

Remove pull-up/down from PA[4] input

SleepCntDis

0 por

R/W

Disable Sleep Reset Counter when Hi

SCRsel1

0 por

R/W

Selection bit 1 for Sleep RCWake-Up period

SCRsel0

0 por

R/W

Selection bit 0 for Sleep RCWake-Up period

Table 4.4.3 Wake-Up period from Sleep selection

SCRsel1

SCRsel0

Sleep Reset Counter periods

1.5 internal low speed RC clock periods

15.5 internal low speed RC clock periods

127.5 internal low speed RC clock periods

1023.5 internal low speed RC clock periods

Refer to table 18.8 or the actual SCR timeout period timings

Sleep Counter Reset (SCR) uses the same prescaler (see chapter 5.3) as the System Clock in Active and

StandBy mode. Prescaler reset is made automatically just before going into Sleep mode if SCR is enable.

This causes the Sleep Reset Counter to have its specified period.

4.5 Wake-Up on Change

By writing the WUchEn[0/5] and/or WUchEn[3/4] bit in RegPaCntl2 registers the PA[0] or PA[5] and/or PA[3]

or PA[4] can generate a reset from sleep on any polarity change on a selected pin. The port selection is

defined with bits IrqPA[0l/5h] and IrqPA[3l/4h]. See chapter 6 and Figure 10 for more details.

4.6 The CPU State after Reset

Reset initializes the CPU as shown in Table 4.6.1 below.

Table 4.6.1 Initial CPU value after Reset.

Name

Bits

Symbol

Initial Value

Program counter 0

PC0

$000 (as a result of Jump 0)

Program counter 1

PC1

Undefined

Program counter 2

PC2

Undefined

Stack pointer

SP[0] selected

Index register

Undefined

Carry flag

Undefined

Zero flag

Undefined

Halt

HALT

Instruction register

Jump 0

Periphery registers

Reg.....

See peripheral memory map

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