X98021 datasheet(15/29 Pages) RENESAS

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X98021

FN8219 Rev 3.00

Page 15 of 29

March 8, 2006

Technical Highlights

The X98021 provides all the features of traditional triple

channel video AFEs, but adds several next-generation

enhancements, bringing performance and ease of use to new

levels.

DPLL

All video AFEs must phase lock to an HSYNC signal, supplied

either directly or embedded in the video stream (Sync On

Green). Historically this function has been implemented as a

traditional analog PLL. At SXGA and lower resolutions, an

analog PLL solution has proven adequate, if somewhat

troublesome (due to the need to adjust charge pump currents,

VCO ranges and other parameters to find the optimum trade-

off for a wide range of pixel rates).

As display resolutions and refresh rates have increased,

however, the pixel period has decreased. An XGA pixel at a

60Hz refresh rate has 15.4ns to change and settle to its new

value. But at UXGA 75Hz, the pixel period is 4.9ns. Most

consumer graphics cards spend most of that time slewing to

the new pixel value. The pixel may settle to its final value with

1ns or less before it begins slewing to the next pixel. In many

cases it never settles at all. So precision, low-jitter sampling is

a fundamental requirement at these speeds, and a difficult one

for an analog PLL to meet.

The X98021's DPLL has less than 250ps of jitter, peak to peak,

and independent of the pixel rate. The DPLL generates 64

phase steps per pixel (vs. the industry standard 32), for fine,

accurate positioning of the sampling point. The crystal-locked

NCO inside the DPLL completely eliminates drift due to charge

pump leakage, so there is inherently no frequency or phase

change across a line. An intelligent all-digital loop

filter/controller eliminates the need for the user to have to

program or change anything (except for the number of pixels)

to lock over a range from interlaced video (10MHz or higher) to

UXGA 75Hz (210MHz).

The DPLL eliminates much of the performance limitations and

complexity associated with noise-free digitization of high speed

signals.

Automatic Black Level Compensation (ABLC™) and

Gain Control

Traditional video AFEs have an offset DAC prior to the ADC, to

both correct for offsets on the incoming video signals and

add/subtract an offset for user “brightness control”. This

solution is adequate, but it places significant requirements on

the system's firmware, which must execute a loop that detects

the black portion of the signal and then servos the offset DACs

until that offset is nulled (or produces the desired ADC output

code). Once this has been accomplished, the offset (both the

offset in the AFE and the offset of the video card generating the

signal) is subject to drift - the temperature inside a monitor or

projector can easily change 50°C between power-on/offset

calibration on a cold morning and the temperature reached

once the monitor and the monitor's environment have reached

steady state. Offset can drift significantly over 50°C, reducing

0x1B

Power Control (0x00)

Red

Power-down

0 = Red ADC operational (default)

1 = Red ADC powered down

Green

Power-down

0 = Green ADC operational (default)

1 = Green ADC powered down

2Blue

Power-down

0 = Blue ADC operational (default)

1 = Blue ADC powered down

3PLL

Power-down

0 = PLL operational (default)

1 = PLL powered down

7:4

Reserved

Set to 0

0x1C

Reserved (0x47)

7:0

Reserved

Set to 0x49 for best performance with NTSC and PAL video

0x23

DC Restore Clamp (0x08)

3:0

Reserved

Set to 1000

6:4

DC Restore Clamp

Impedance

DC Restore clamp's ON resistance.

Shared for all three channels

0: Infinite (clamp disconnected) (default)

1: 1600



2: 800



3: 533



4: 400



5: 320



6: 267



7: 228



Reserved

Set to 0

ADDRESS

BIT(s)

FUNCTION NAME

DESCRIPTION

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