HT46C47 datasheet(13/39 Pages) HOLTEK

13 / 39 page

HT46R47/HT46C47

Rev. 1.30

May 3, 2004

Label (TMRC)

Bits

Function

PSC0~PSC2

0~2

To define the prescaler stages, PSC2, PSC1, PSC0=

000: fINT=fSYS

001: fINT=fSYS/2

010: fINT=fSYS/4

011: fINT=fSYS/8

100: fINT=fSYS/16

101: fINT=fSYS/32

110: fINT=fSYS/64

111: fINT=fSYS/128

To define the TMR active edge of the Timer/Event Counter

(0=active on low to high; 1=active on high to low)

TON

To enable or disable timer counting

(0=disabled; 1=enabled)

Unused bits, read as

²0²

TM0

TM1

To define the operating mode

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

TMRC Register

T M 1

T M 0

T M R

T E

T M 1

T M 0

T O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

8 - B i t T i m e r / E v e n t

C o u n t e r P r e l o a d

R e g i s t e r

8 - B i t T i m e r / E v e n t

C o u n t e r

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

1 / 2

P F D

8 - s t a g e P r e s c a l e r

8 - 1 M U X

f S Y S

f I N T

P S C 2 ~ P S C 0

( 6 + 2 ) C o m p a r e

P W M

T o P D 0 C i r c u i t

Timer/Event Counter

In the pulse width measurement mode with the TON

and TE bits equal to one, once the TMR has received a

transient from low to high (or high to low if the TE bits is

²0²) it will start counting until the TMR returns to the orig-

inal level and resets the TON. The measured result will

remain in the timer/event counter even if the activated

transient occurs again. In other words, only one cycle

measurement can be done. Until setting the TON, the

cycle measurement will function again as long as it re-

ceives further transient pulse. Note that, in this operat-

ing mode, the timer/event counter starts counting not

according to the logic level but according to the transient

edges. In the case of counter overflows, the counter is

reloaded from the timer/event counter preload register

and issues the interrupt request just like the other two

modes. To enable the counting operation, the timer ON

bit (TON; bit 4 of TMRC) should be set to 1. In the pulse

width measurement mode, the TON will be cleared au-

tomatically after the measurement cycle is completed.

But in the other two modes the TON can only be reset by

instructions. The overflow of the timer/event counter is

one of the wake-up sources. No matter what the opera-

tion mode is, writinga0toETIcan disable the interrupt

service.

In the case of timer/event counter OFF condition, writ-

ing data to the timer/event counter preload register will

also reload that data to the timer/event counter. But if the

timer/event counter is turned on, data written to it will

only be kept in the timer/event counter preload register.

The timer/event counter will still operate until overflow oc-

curs. When the timer/event counter (reading TMR) is read,

the clock will be blocked to avoid errors. As clock blocking

may results in a counting error, this must be taken into con-

sideration by the programmer.

The bit0~bit2 of the TMRC can be used to define the

pre-scaling stages of the internal clock sources of

timer/event counter. The definitions are as shown. The

overflow signal of timer/event counter can be used to

generate the PFD signal.

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