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LTC2622CMS8 Scheda tecnica(PDF) 3 Page - Linear Technology |
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LTC2622CMS8 Scheda tecnica(HTML) 3 Page - Linear Technology |
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3 / 16 page ![]() 3 LTC2602/LTC2612/LTC2622 2602f ELECTRICAL C C HARA TERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted. LTC2602/LTC2612/LTC2622 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS PSRR Power Supply Rejection Ratio VCC = 5V ±10% –80 dB ROUT DC Output Impedance VREF = VCC = 5V, Midscale; –15mA ≤ IOUT ≤ 15mA q 0.05 0.15 Ω VREF = VCC = 2.5V, Midscale; –7.5mA ≤ IOUT ≤ 7.5mA q 0.05 0.15 Ω DC Crosstalk (Note 4) Due to Full Scale Output Change (Note 5) ±30 µV Due to Load Current Change ±16 µV/mA Due to Powering Down (per Channel) ±4 µV ISC Short-Circuit Output Current VCC = 5.5V, VREF = 5.5V Code: Zero Scale; Forcing Output to VCC q 15 34 60 mA Code: Full Scale; Forcing Output to GND q 15 38 60 mA VCC = 2.5V, VREF = 2.5V Code: Zero Scale; Forcing Output to VCC q 7.5 20 50 mA Code: Full Scale; Forcing Output to GND q 7.5 28 50 mA Reference Input Input Voltage Range q 0VCC V Resistance Normal Mode q 44 64 80 k Ω Capacitance 23 pF IREF Reference Current, Power Down Mode All DACs Powered Down q 0.001 1 µA Power Supply VCC Positive Supply Voltage For Specified Performance q 2.5 5.5 V ICC Supply Current VCC = 5V (Note 3) q 0.7 1.3 mA VCC = 3V (Note 3) q 0.6 1 mA All DACs Powered Down (Note 3) VCC = 5V q 0.35 1 µA All DACs Powered Down (Note 3) VCC = 3V q 0.10 1 µA Digital I/O VIH Digital Input High Voltage VCC = 2.5V to 5.5V q 2.4 V VCC = 2.5V to 3.6V q 2.0 V VIL Digital Input Low Voltage VCC = 4.5V to 5.5V q 0.8 V VCC = 2.7V to 5.5V q 0.6 V VCC = 2.5V to 5.5V q 0.5 V ILK Digital Input Leakage VIN = GND to VCC q ±1 µA CIN Digital Input Capacitance (Note 6) q 8pF LTC2622 LTC2612 LTC2602 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS AC Performance ts Settling Time (Note 8) ±0.024% (±1LSB at 12 Bits) 7 7 7 µs ±0.006% (±1LSB at 14 Bits) 9 9 µs ±0.0015% (±1LSB at 16 Bits) 10 µs Settling Time for ±0.024% (±1LSB at 12 Bits) 2.7 2.7 2.7 µs 1LSB Step (Note 9) ±0.006% (±1LSB at 14 Bits) 4.8 4.8 µs ±0.0015% (±1LSB at 16 Bits) 5.2 µs Voltage Output Slew Rate 0.80 0.80 0.80 V/ µs Capacitive Load Driving 1000 1000 1000 pF Glitch Impulse At Midscale Transition 12 12 12 nV • s Multiplying Bandwidth 180 180 180 kHz en Output Voltage Noise At f = 1kHz 120 120 120 nV/ √Hz Density At f = 10kHz 100 100 100 nV/ √Hz Output Voltage Noise 0.1Hz to 10Hz 15 15 15 µVP-P |
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