SSM6322ACPZ-R2 datasheet(15/20 Pages) AD

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Data Sheet

SSM6322

Rev. 0 | Page 15 of 20

THEORY OF OPERATION

The SSM6322 is designed using Analog Devices, Inc., proprietary

extra fast complementary bipolar (XFCB) process. The device

features exceptionally low 1/f noise, low power, and load drive

capability. The device combines a classic difference amplifier

configuration with a common-mode loop that maintains a fixed

common-mode input level, regardless of the differential or

common-mode currents going into the device. This combination

results in the DAC operating in optimal conditions to reach the

THD specifications. This configuration of a common-mode

loop and a difference amplifier also has much lower noise and

power consumption than other solutions by eliminating two

additional amplifiers from the signal path.

The output driver has many features including heavy load drive,

multiplexing, and pop click suppression. In both shutdown

conditions, the output is high impedance in the audio band

when the applied external signal is between the supply rails.

An additional shutdown pin is included to power up the input

difference amplifier so that it can settle before any unwanted

signals are applied to the driver. The output driver is capable of

delivering −120 dB THD with a 100 mA peak output current

and a 2 V rms signal.

REF1 and REF2 Pin Voltage

REF1 and REF2 set the input common-mode signal. Internally,

there is a 15 μA current source; by externally adding a resistor,

15 μA of current flows through the resistor to generate a

common-mode voltage. For example, a 51 kΩ resistor and

15 μA current results in a common-mode voltage of 0.765 V.

Shutdown Control

The SSM6322 features two shutdown pins to control different

sections of the device. When SD and SD2 are Logic 1, the entire

device is enabled. When SD is Logic 0 and SD2 is Logic 1, the

input stage is enabled, and the output buffer is disabled. When

SD2 is Logic 0, the entire device is disabled with a quiescent

current of only 15 μA (see Table 6).

Table 6. Disabled Mode and Enabled Mode

Logic Level of the

Shutdown Pins

Device Status

SD and SD2 = 1

Entire device is enabled.

SD = 0 and SD2 = 1

Input stage is enabled, and the output

buffer is disabled.

SD2 = 0

Entire device is disabled with a quiescent

current of 15 μA.

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