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TAS5000 Scheda tecnica(PDF) 16 Page - Texas Instruments

Il numero della parte TAS5000
Spiegazioni elettronici  DIGITAL AUDIO PWM PROCESSOR
PDF  24 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

TAS5000 Scheda tecnica(HTML) 16 Page - Texas Instruments

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2–6
•
Left channel is received when LRCLK is low.
•
Right channel is received when LRCLK is high.
•
SDIN is sampled with the rising edge of SCLK.
2.8.3
MSB Left Justified Serial Interface Format (for 16 bits)
MSB
LSB
MSB
LSB
SCLK
LRCLK = Fs
SDIN
Left Channel
Right Channel
Figure 2–8. MSB Left Justified Serial Interface Format
Note the following characteristics of this protocol.
•
Left channel is received when LRCLK is high.
•
Right channel is received when LRCLK is low.
•
The SDIN data is justified to the leading edge of the LRCLK.
•
SDIN is sampled with the rising edge of SCLK.
2.8.4
DSP Compatible Serial Interface Format (for 16 bits)
SCLK
LRCLK = Fs
SDIN
Left Channel
(MSB = 15)
Right Channel
(MSB = 15)
15
14
13
0
15
14
13
0
Figure 2–9. DSP Compatible Serial Interface Format
Note the following characteristics of this protocol.
•
Serial data is sampled with the falling edge of SCLK.
2.9
PWM Outputs
Designed to be used with TAS5100.



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