ICS8305 datasheet(1/17 Pages) IDT

Il numero della parte	ICS8305

Spiegazioni elettronici	Low Skew, 1-to-4 Multiplexed Differential/LVCMOS-to-LVCMOS/LVTTL Fanout Buffer

PDF	17 Pages

Scroll/Zoom	100%

Produttore elettronici	IDT [Integrated Device Technology]

Homepage	http://www.idt.com

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1 / 17 page

Low Skew, 1-to-4 Multiplexed Differential/

LVCMOS-to-LVCMOS/LVTTL Fanout Buffer

ICS8305AG REVISION C MAY 30, 2014

1

DATA SHEET

ICS8305

General Description

The ICS8305 is a low skew, 1-to-4, Differential/ LVCMOS-to-

LVCMOS/LVTTL Fanout Buffer. The ICS8305 has selectable clock

inputs that accept either differential or single ended input levels. The

clock enable is internally synchronized to eliminate runt pulses on

the outputs during asynchronous assertion/deassertion of the clock

enable pin. Outputs are forced LOW when the clock is disabled. A

separate output enable pin controls whether the outputs are in the

active or high impedance state.

Guaranteed output and part-to-part skew characteristics make the

ICS8305 ideal for those applications demanding well defined

performance and repeatability.

Features

• Four LVCMOS / LVTTL outputs, 7 output impedance

• Selectable differential or LVCMOS / LVTTL clock inputs

• CLK, nCLK pair can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, HCSL, SSTL

• LVCMOS_CLK supports the following input types: LVCMOS,

LVTTL

• Maximum output frequency: 350MHz

• Output skew: 35ps (maximum)

• Part-to-part skew: 700ps (maximum)

• Additive phase jitter, RMS: 0.04ps (typical)

• Power supply modes:

Core/Output

3.3V/3.3V

3.3V/2.5V

3.3V/1.8V

3.3V/1.5V

• 0°C to 70°C ambient operating temperature

• Available in lead-free (RoHS 6) package

Block Diagram

Pin Assignment

ICS8305

16-Lead TSSOP

4.4mm x 3.0mm x 0.925mm package body

G Package

Top View

LVCMOS_CLK

CLK

nCLK

CLK_SEL

Q0

Q1

Q2

Q3

0

1

CLK_EN

OE

D

Q

LE

0

1

Pullup

Pulldown

Pullup/

Pulldown

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

LVCMOS_CLK

CLK_SEL

nCLK

CLK

CLK_EN

VDD

OE

GND

Q0

VDDO

Q1

GND

Q2

VDDO

Q3

GND

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