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FSUSB40 Scheda tecnica(PDF) 10 Page - ON Semiconductor |
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FSUSB40 Scheda tecnica(HTML) 10 Page - ON Semiconductor |
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10 / 12 page ![]() © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSUSB40 • Rev. 1.0.8 9 Physical Dimensions A. DIMENSIONS ARE IN MILLIMETERS. B. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 TOP VIEW BOTTOM VIEW RECOMMENDED LAND PATTERN 0.15 C 0.08 C B A C 0.15 C 2X 2X SIDE VIEW SEATING PLANE 0.10 C 0.050 3 6 1 0.10 C A B 0.05 C 0.55 MAX. PIN #1 QUADRANT 10 1.40 1.80 0.40 0.15 0.25 10X 0.45 0.55 0.35 0.45 9X 1.700 2.100 0.400 0.663 0.563 9X 0.225 10X 1 0.152 0.100 0.100 0.500 0.100 DETAIL A PIN #1 TERMINAL SCALE: 2X 1.850 1.450 0.550 0.400 0.225 10X 9X 0.450 OPTIONAL MINIMIAL TOE LAND PATTERN C. DRAWING FILENAME: UMLP10Arev2 Figure 17. 10-Lead, Ultrathin Molded Leadless Package (UMLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. |
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