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MMPF0100Z Scheda tecnica(PDF) 18 Page - NXP Semiconductors |
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MMPF0100Z Scheda tecnica(HTML) 18 Page - NXP Semiconductors |
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18 / 128 page ![]() 18 NXP Semiconductors PF0100Z FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS VGEN5_VOLT 2.5 V 2.8 V 3.3 V 2.8 V 2.5 V 2.5 V VGEN5_SEQ 3 12 5 -8 8 VGEN6_VOLT 2.8 V 3.3 V 3.0 V 2.8 V 2.8 V 2.8 V VGEN6_SEQ 3 8 1 67 7 PU CONFIG, SEQ_CLK_SPEED 1.0 ms 2.0 ms 0.5 ms 2.0 ms 0.5 ms 0.5 ms PU CONFIG, SWDVS_CLK 6.25 mV/ μs 1.5625 mV/ μs 6.25 mV/ μs 25 mV/16 μs6.25 mV/μs 6.25 mV/ μs PU CONFIG, PWRON Level sensitive SW1AB CONFIG SW1AB Single Phase, SW1C Independent Mode, 2.0 MHz SW1ABC Single Phase, 2.0 MHz SW1C CONFIG 2.0 MHz SW2 CONFIG 2.0 MHz SW3A CONFIG SW3AB Single Phase, 2.0 MHz SW3B CONFIG 2.0 MHz SW4 CONFIG No VTT, 2.0 MHz PG EN RESETBMCU in Default Mode Table 9. Start-up configuration (continued) Registers Default configuration Pre-programmed OTP configuration All devices F0 F6 F8 F9 FA |
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