LTC6953 datasheet(31/56 Pages) AD

Il numero della parte	LTC6953

Spiegazioni elettronici	Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B Support

PDF	56 Pages

Scroll/Zoom	100%

Produttore elettronici	AD [Analog Devices]

Homepage	http://www.analog.com

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31 / 56 page

LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Figure 21. Common EZS_SRQ Input Interface Configurations. All ZO Signal Traces Are 50Ω Transmission Lines

750Ω

50Ω

100Ω

130Ω

100Ω

150Ω

DC-COUPLED DIFFERENTIAL LVDS

LTC6953

LVDS

6953 F21

LTC6953

CML

DC-COUPLED DIFFERENTIAL CML*

LTC6953

1.8V TO 3.3V

CMOS

1.8V TO 3.3V CMOS

3.3V

LTC6953

LVPECL

DC-COUPLED DIFFERENTIAL LVPECL*

* OUTPUT COMMON MODE LEVELS OF DIFFERENTIAL DRIVERS MUST BE

WITHIN THE MIN AND MAX EZS_SRQ INPUT COMMON MODE LEVELS

SPECIFIED IN THE ELECTRICAL CHARACTERISTICS.

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

–

EZS_SRQ INPUT

The LTC6953’s EZS_SRQ input buffer, shown in Figure 4,

controls synchronization requests and SYSREF requests.

All connections

MUST be DC-coupled and can be either

differential CML or LVPECL, differential LVDS with a level-

shifting network or single-ended 1.8V to 3.3V CMOS into

the EZS_SRQ+ input pin (EZS_SRQ– must be grounded

for CMOS drive). Figure 21 shows the recommended

interface types.

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