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HT46R63 Scheda tecnica(PDF) 4 Page - Holtek Semiconductor Inc |
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HT46R63 Scheda tecnica(HTML) 4 Page - Holtek Semiconductor Inc |
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4 / 44 page ![]() Pad Assignment HT46C63 * The IC substrate should be connected to VSS in the PCB layout artwork. Pin Description Pin Name I/O Option Description PA0~PA7 I/O Pull-high Wake-up I/O lines with pull-high resistors (bit option). I/O modes of each line are con- trolled by related control register bit (PAC). Each line of PA can be optioned as a wake-up input (bit option). I/O configurations: Schmitt trigger/CMOS PB0/AN0~ PB7/AN7 I/O Pull-High I/O lines with pull-high resistors (bit option). I/O modes of each line are con- trolled by related control register bit (PBC). I/O configurations: Schmitt trig- ger/CMOS. Each PB line is pin shared with an A/D converter input. PC0~PC6, PC7 I/O Pull-High I/O lines with pull-high resistors (bit option). I/O modes of each line are con- trolled by related control register bit (PCC). I/O configurations: Schmitt trig- ger/CMOS. PD0/PWM0~ PD3/PWM3, PD4/INT0, PD5/INT1, PD6/TMR, PD7 I/O Pull-High PWM Interrupt Falling and/or Rising I/O lines with pull-high resistors (bit option). I/O modes of each line are con- trolled by related control register bit (PDC). I/O configurations: Schmitt trig- ger/CMOS. The PD0~PD3 can be selected as PWM outputs. INT0/INT1 are falling/rising edge selectable triggers. HT46R63/HT46C63 Rev. 1.90 4 May 17, 2004 7 2 1 2 3 4 5 6 7 8 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 6 4 5 4 4 4 3 4 2 4 7 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 0 9 ( 0 , 0 ) P A 0 P A 1 P A 2 P A 3 P A 4 P A 5 P A 6 P A 7 V S S V S S A N 0 / P B 0 A N 1 / P B 1 A N 2 / P B 2 A N 3 / P B 3 A N 4 / P B 4 A N 5 / P B 5 A N 6 / P B 6 A N 7 / P B 7 S E G 6 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 1 2 S E G 1 1 S E G 1 0 S E G 9 S E G 8 S E G 7 S E G 1 3 C O M 3 / S E G 1 9 S E G 1 8 S E G 1 7 S E G 1 6 S E G 1 5 S E G 1 4 C O M 1 C O M 2 |
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