ADF41513 datasheet(13/33 Pages) AD

13 / 33 page

Preliminary Technical Data

ADF41513

Rev. PrL | Page 13 of 33

READBACK

output. In this mode, the MUXOUT line concurrently transfers

32 bits of the previous written register value while clocking in

32 bits of write data.

To read back a specific register, chip revision code, or bit

pattern, write 1000b to Bits[31:28], Register 12. Writing to

Bits[31:28] sets the MUXOUT pin to read back what is selected

by Bits[19:14] in Register 12.

INPUT SHIFT REGISTERS

The ADF41513 contains a programmable digital block. Data is

clocked into the 32-bit shift register on each rising edge of CLK.

The data is clocked in MSB first. Data is transferred from the

shift register to the chosen register on the rising edge of LE. The

destination latch is determined by the state of the four control

bits (C4, C3, C2, and C1) in the shift register. The following are

the four LSBs: DB3, DB2, DB1, and DB0. The truth table for

these bits is shown in Table 5. Figure 18 through Figure 20 show

a summary of how the registers are programmed.

PROGRAM MODES

Table 5 and Figure 21 through Figure 34 show how to set up the

program modes in the ADF41513.

Several settings in the ADF41513 are double buffered. These

include the MOD2, FRAC1, FRAC2, R counter value, reference

doubler, LSB P1, CP, current setting, and RDIV2. Two events

must occur before the device uses a new value for any of the

double buffered settings. First, the new value is latched into the

device by writing to the appropriate register. Second, a new

write must be performed on Register 0. For example, updating

the FRAC1 value requires a write to Register 1 and a write to

Table 5. C3, C2, and C1 Truth Table

Control Bits

R10

R11

R12

R13

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