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PTPS16632RGET Scheda tecnica(PDF) 25 Page - Texas Instruments |
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PTPS16632RGET Scheda tecnica(HTML) 25 Page - Texas Instruments |
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25 / 30 page ![]() TOP Layer GND Plane BOTTOM Layer GND Plane BOTTOM Layer GND Plane Via to Bottom Layer Top Layer Top Layer GND Plane Bottom layer GND plane VOUT PLANE D2 OVP N.C IN P_IN IN SHDN OUT OUT GND N.C ILIM dVdT PGOOD MODE IN N.C UVLO IMON FLT OUT VIN PLANE High Frequency Bypass cap D1 25 TPS1663 www.ti.com SLVSET9A – SEPTEMBER 2018 – REVISED OCTOBER 2018 Product Folder Links: TPS1663 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Layout Example (continued) Figure 20. Typical PCB Layout Example with HTSSOP Package with a 2 Layer PCB |
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