AM652X datasheet(152/299 Pages) TI1

152 / 299 page

MCU_PLL0

(MCU PLL)

SPRSP08_PLL_PWR_01

MCU_PLL1

(CPSW PLL)

PLL0

(MAIN PLL)

PLL2

(PER1 PLL)

PLL1

(PER0 PLL)

PLL3

(DDR PLL)

PLL4

(DSS PLL)

PLL6

(ARM0 PLL)

PLL7

(ARM1 PLL)

VDDA_MCU

VDDA_PLL_CORE

VDDA_PLL_PER0

VDDA_PLL0_DDR

VDDA_PLL_DSS

VDDA_PLL_MPU0

VDDA_PLL_MPU1

152

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Specifications

Figure 5-25. PLL Power Supply Connectivity

Table 5-26 provides the power supply requirements for the PLL.

Table 5-26. PLL Power Supply Requirements

SUPPLY NAME

DESCRIPTION

MIN

NOM

MAX

UNIT

VDD_DLL_MMC0

MMC0 PHY DLL voltage supply

0.95

1.05

Max. peak-to-peak supply noise

TBD

mV (p-p)

VDD_DLL_MMC1

MMC1 PHY DLL voltage supply

0.95

1.05

Max. peak-to-peak supply noise

TBD

mV (p-p)

VDDA_PLL_CORE

CORE DPLL, PER1 DPLL analog power supply

1.71

1.8

1.89

Max. peak-to-peak supply noise

mV (p-p)

VDDA_PLL0_DDR

DDR DPLL analog power supply

1.71

1.8

1.89

Max. peak-to-peak supply noise

mV (p-p)

VDDA_PLL1_DDR

DDR De-skew DPLL analog power supply

1.71

1.8

1.89

Max. peak-to-peak supply noise

mV (p-p)

VDDA_PLL_DSS

DSS DPLL analog power supply

1.71

1.8

1.89

Max. peak-to-peak supply noise

mV (p-p)

VDDA_PLL_MPU0

MPU0 DPLL analog power supply

1.71

1.8

1.89

Max. peak-to-peak supply noise

mV (p-p)

VDDA_PLL_MPU1

MPU1 DPLL analog power supply

1.71

1.8

1.89

Max. peak-to-peak supply noise

mV (p-p)

VDDA_PLL_PER0

PER0 DPLL analog power supply

1.71

1.8

1.89

Max. peak-to-peak supply noise

mV (p-p)

5.11.4.4 System Clocks Operating Frequency Ranges

Table 5-27 lists the operating frequency ranges for the system clocks of the device.

Table 5-27. System Clocks Operating Frequency Range

System Clocks (1)

Bypass Min

(MHz)

Bypass Max

(MHz)

Minimum Operating Frequency

(MHz)

PLL0 (MAIN PLL)

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