M8888-R1 datasheet(7/14 Pages) CLARE

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Staus Register Description

Bit

Name

Status Flag Set

Status Flag Cleared

IRQ

Interrupt has occurred. Bit one (b1)

Interrupt is inactive. Cleared after

and/or bit 2 (b2) is set.status register is read.

Transmit data register empty

Pause duration has terminated and transmitter

Cleared after status register is read or

(burst mode only)

is ready for new data.

when not in burst mode.

Receive data register full.

Valid data is in the receive data register.

Cleared after status register is read.

Delayed Steering

Set on valid detection of the absence of a

Cleared on detection of a valid DTMF

DTMF signal.

signal.

RSEL

IRQ

CP/DTMF

TOUT

M-8888

www.clare.com

Rev. 1

Common Crystal Connection

RS0

Function

Write to transmitter

Read from receiver

Write to control register

Read from status register

Internal Register Functions

CRA Bit Positions

C/R

S/D

TEST

BURST

CRB Bit Positions

Equations

Application Circuit (Single-Ended Input)

M8888-R1 Scheda tecnica(PDF) 7 Page - Clare, Inc.

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