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IC-MU200 Scheda tecnica(PDF) 3 Page - IC-Haus GmbH |
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IC-MU200 Scheda tecnica(HTML) 3 Page - IC-Haus GmbH |
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3 / 65 page ![]() iC-MU200 MAGNETIC OFF-AXIS POSITION ENCODER - POLE WIDTH 2.00MM Rev A1, Page 3/65 CONTENTS PACKAGING INFORMATION 5 PIN CONFIGURATION QFN48-7x7 (topview) . . . . . . . . . . . . . . . . . 5 PACKAGE DIMENSIONS QFN48-7x7 . . . . 6 ABSOLUTE MAXIMUM RATINGS 7 THERMAL DATA 7 ELECTRICAL CHARACTERISTICS 8 OPERATING REQUIREMENTS 10 Multiturn Interface . . . . . . . . . . . . . . . 10 I/O Interface . . . . . . . . . . . . . . . . . . 11 PRINCIPLE OF MEASUREMENT 13 Rotative measuring system . . . . . . . . . . 13 Linear measuring system . . . . . . . . . . . 13 CONFIGURATION PARAMETERS 14 REGISTER ASSIGNMENTS (EEPROM) 16 Register assignment (EEPROM) . . . . . . . 16 Special BiSS registers . . . . . . . . . . . . . 18 SIGNAL CONDITIONING FOR MASTER AND NONIUS CHANNELS: x = M,N 19 Bias current source . . . . . . . . . . . . . . 19 Gain settings . . . . . . . . . . . . . . . . . . 19 Offset compensation . . . . . . . . . . . . . . 20 Phase adjustment . . . . . . . . . . . . . . . 20 ANALOG SIGNAL CONDITIONING FLOW: x = M,N 21 1. Conditioning the BIAS current . . . . . . . 21 2. Positioning of the sensor . . . . . . . . . . 21 3.a Test modes analog master and analog nonius . . . . . . . . . . . . . . . . . . . 21 3.b Test mode CNV_x . . . . . . . . . . . . . 21 4. Track offset SPON . . . . . . . . . . . . . 22 EEPROM AND I2C INTERFACE 23 Basic interface features . . . . . . . . . . . . 23 EEPROM device requirements . . . . . . . . 23 CRC checksums . . . . . . . . . . . . . . . . 23 STARTUP BEHAVIOR 25 CONFIGURABLE I/O INTERFACE 27 Setting the interfaces . . . . . . . . . . . . . 27 Serial interface: Configuring the data format and data length . . . . . . . . . . . . . . . . . . . 28 BiSS C interface . . . . . . . . . . . . . . . . 30 SSI interface . . . . . . . . . . . . . . . . . . 31 SPI interface: general description . . . . . . . 33 SPI interface: Command ACTIVATE . . . . . 33 SPI interface: Command SDAD transmission 34 SPI interface: Command SDAD status . . . . 35 SPI interface: Command Read REGISTER (single) . . . . . . . . . . . . . . . . . . 35 SPI interface: Command Write REGISTER (single) . . . . . . . . . . . . . . . . . . 36 SPI interface: Command REGISTER status/data . . . . . . . . . . . . . . . . 36 CONVERTER AND NONIUS CALCULATION 38 Converter principle . . . . . . . . . . . . . . . 38 Synchronization mode . . . . . . . . . . . . . 38 MT INTERFACE 41 Configuration of the Multiturn interface . . . . 41 Construction of a Multiturn system with two iC-MU200 . . . . . . . . . . . . . . . . . 42 MT Interface Daisy Chain . . . . . . . . . . . 44 INCREMENTAL OUTPUT ABZ, STEP/DIRECTION AND CW/CCW 45 UVW COMMUTATION SIGNALS 48 REGISTER ACCESS THROUGH SERIAL INTERFACE (SPI AND BISS) 49 Register mapping Configuration, Bank 0: Addresses 0x00-0x3F . . . . . . . . . . 49 Register mapping static part: Addresses 0x40-0xBF . . . . . . . . . . . . . . . . 51 Address sections/Register protection level . . 53 Overview Register access: memory mapping, Register protection levels . . . . . . . . 54 STATUS REGISTER AND ERROR MONITORING 55 Status register . . . . . . . . . . . . . . . . . 55 Error and warning bit configuration . . . . . . 55 COMMAND REGISTER 57 |
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