ICS8735-01 datasheet(7/17 Pages) ICST

7 / 17 page

8735AY-01

www.icst.com/products/hiperclocks.html

REV. F NOVEMBER 12, 2004

Integrated

Circuit

Systems, Inc.

ICS8735-01

1:5 DIFFERENTIAL-TO-3.3V LVPECL

ZERO DELAY CLOCK GENERATOR

APPLICATION INFORMATION

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

CC/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin.The ratio

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

CC = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

V_REF

0.1u

Single Ended Clock Input

CLKx

nCLKx

VCC

CC - 2V

Ω

RTT

o = 50Ω

FOUT

FIN

RTT =

((V

OH + VOL) / (VCC – 2)) – 2

3.3V

125

Ω

125

Ω

o = 50Ω

FOUT

FIN

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that gen-

erate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must

be used for functionality. These outputs are designed to drive

Ω transmission lines. Matched impedance techniques should

be used to maximize operating frequency and minimize signal

distortion.

Figures 1A and 1B show two different layouts which

are recommended only as guidelines. Other suitable clock lay-

outs may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

FIGURE 1B. LVPECL OUTPUT TERMINATION

FIGURE 1A. LVPECL OUTPUT TERMINATION

TERMINATION FOR LVPECL OUTPUTS

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