INA821 datasheet(28/41 Pages) TI1

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10 k

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10 k

24.7 k

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RREF

INA821

SBOS893A – AUGUST 2018 – REVISED DECEMBER 2018

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Reference Pin

The output voltage of the INA821 is developed with respect to the voltage on the reference pin (REF.) Often in

dual-supply operation, the reference pin (pin 6) connects to the low-impedance system ground. In single-supply

operation, offsetting the output signal to a precise midsupply level is useful (for example, 2.5 V in a 5-V supply

environment). To accomplish this level shift, a voltage source must be connected to the REF pin to level-shift the

output so that the INA821 drives a single-supply ADC.

The voltage source applied to the reference pin must have a low output impedance. As shown in Figure 65, any

resistance at the reference pin ( RREF in Figure 65) is in series with one of the internal 10-kΩ resistors.

Figure 65. Parasitic Resistance Shown at the Reference Pin

The parasitic resistance at the reference pin (RREF) creates an imbalance in the four resistors of the internal

difference amplifier, resulting in degraded common-mode rejection ratio (CMRR). Figure 66 shows the

degradation in CMRR of the INA821 for increasing resistance at the reference pin. For the best performance,

keep the source impedance to the REF pin (RREF) below 5 Ω.

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