MCP6291IDBVR datasheet(22/40 Pages) TI1

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OUT A

-IN A

+IN A

V±

OUT B

-IN B

+IN B

V+

VS±

GND

Ground (GND) plane on another layer

Keep input traces short

and run the input traces

as far away from

the supply lines

as possible.

Place components

close to device and to

each other to reduce

parasitic errors.

Use low-ESR,

ceramic bypass

capacitor. Place as

close to the device

as possible.

VIN A

GND

VIN B

GND

VS+

GND

OUT A

OUT B

Use low-ESR,

ceramic bypass

capacitor. Place as

close to the device

as possible.

VIN B

VOUT B

VIN A

VOUT A

MCP6291, MCP6292, MCP6294

SBOS879C – JULY 2017 – REVISED JANUARY 2019

www.ti.com

Product Folder Links: MCP6291 MCP6292 MCP6294

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11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp

itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the

analog circuitry.

–

Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground

planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise

pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the

ground current. For more detailed information, see Circuit Board Layout Techniques.

•

To reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much

better as opposed to in parallel with the noisy trace.

•

Place the external components as close to the device as possible. As shown in Figure 37, keeping RF

and RG close to the inverting input minimizes parasitic capacitance on the inverting input.

•

Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

•

Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly

reduce leakage currents from nearby traces that are at different potentials.

•

Cleaning the PCB following board assembly is recommended for best performance.

•

Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the

plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is

recommended to remove moisture introduced into the device packaging during the cleaning process. A

low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

11.2 Layout Example

Figure 36. Schematic Representation for Figure 37

Figure 37. Layout Example

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