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DSP56857 Scheda tecnica(PDF) 365 Page - Freescale Semiconductor, Inc

Il numero della parte DSP56857
Spiegazioni elettronici  Digitial Signal Controller
PDF  662 Pages
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Produttore elettronici  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56857 Scheda tecnica(HTML) 365 Page - Freescale Semiconductor, Inc

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User Notes
Enhanced Synchronous Serial Interface (ESSI), Rev. 4
Freescale Semiconductor
12-65
12.13.6 Transmit Last Slot (TLS)
This interrupt occurs when the ESSI is in the Network mode at the beginning of the last slot of
the transmit frame. The TLS bit is also set at this time. This exception occurs regardless of the
Transmit Mask Register setting. This interrupt and the TLS bit are cleared by writing 1 to the
TLS bit of the SSR.
12.14 User Notes
12.14.1 External Frame Sync Setup
When using external frame syncs, there must be at least four clocks after enabling the
transmitter/receiver and before the first frame sync.
12.14.2 Maximum External Clock Rate
The maximum allowable rate for an external clock source is one fourth of the peripheral clock.



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