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DSP56857 Scheda tecnica(PDF) 414 Page - Freescale Semiconductor, Inc |
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DSP56857 Scheda tecnica(HTML) 414 Page - Freescale Semiconductor, Inc |
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414 / 662 page ![]() Register Descriptions 5685X Digital Signal Controller User Manual, Rev. 4 15-14 Freescale Semiconductor 15.8.9 Port A Data Direction Register (GPIOA_DDR) Figure 15-18. Port A Data Direction Register (GPIOA_DDR) See Programmer’s Sheet on Appendix page B - 113 15.8.9.1 Reserved—Bits 15–4 These bits are reserved or not implemented. They are read as 0 and cannot be modified by writing. 15.8.9.2 Data Direction (DD)—Bits 3–0 These bits control the pins direction when in GPIO mode. These bits have no effect on the output enables or pull-up enables in the Normal mode. • 0 = Pin is an input; pull-ups are dependent on value of PUE registers (default) • 1 = Pin is an output; pull-ups are disabled 15.8.10 Port B Data Direction Register (GPIOB_DDR) Figure 15-19. Port B Direction Register (GPIOB_DDR) See Programmer’s Sheet on Appendix page B - 114 15.8.10.1 Data Direction (DD)—Bits 15–0 These bits control the pins direction when in GPIO mode. These bits have no effect on the output enables or pull-up enables in the Normal mode. • 0 = Pin is an input; pull-ups are dependent on value of PUE registers (default) • 1 = Pin is an output; pull-ups are disabled Base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 0 0 DD Write Reset 000 000 00 0 0 0 0 0 0 0 0 Base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read DD Write Reset 000 000 00 0 0 0 0 0 0 0 0 |
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