DSP56857 datasheet(417/662 Pages) FREESCALE

417 / 662 page

General Purpose Input/Output (GPIO), Rev. 4

Freescale Semiconductor

15-17

15.8.15 Port G Data Direction Register (GPIOG_DDR)

Figure 15-24. Port G Direction Register (GPIOG_DDR)

See Programmer’s Sheet on Appendix page B - 119

15.8.15.1 Reserved—Bits 15–4

These bits are reserved or not implemented. They are read as 0 and cannot be modified by

writing.

15.8.15.2 Data Direction (DD)—Bits 3–0

These bits control the pins direction when in the GPIO mode. These bits have no effect on the

output enables or pull-up enables in the Normal mode.

•

0 = Pin is an input; pull-ups are dependent on value of PUE registers (default)

•

1 = Pin is an output; pull-ups are disabled

15.8.16 Port H Data Direction Register (GPIOH_DDR)

Figure 15-25. Port H Direction Register (GPIOH_DDR)

See Programmer’s Sheet on Appendix page B - 120

15.8.16.1 Reserved—Bits 15–3

These bits are reserved or not implemented. They are read as 0 and cannot be modified by

writing.

15.8.16.2 Data Direction (DD)—Bits 2–0

These bits control the pins direction when in the GPIO mode. These bits have no effect on the

output enables or pull-up enables in the Normal mode.

•

0 = Pin is an input; pull-ups are dependent on value of PUE registers (default)

•

1 = Pin is an output; pull-ups are disabled

Base + $1

Read

Write

Reset

000

Base + $1

Read

Write

Reset

00000

000

DSP56857 Scheda tecnica(PDF) 417 Page - Freescale Semiconductor, Inc