FXLP34 datasheet(9/14 Pages) ONSEMI

9 / 14 page

www.fairchildsemi.com

FXLP34 • Rev. 1.0.4

Translator Power-up Sequence Recommendations

To ensure that the system does not experience

unnecessary ICC current draw, bus contention, or

oscillations during power-up; adhere to the following

guidelines. This device is designed with the output pin(s)

supplied by VCC and the input pin(s) supplied by VCC1.

The first recommendation is to begin by powering up the

input side of the device with VCC1. The Input pin(s)

should be ramped with or ahead of VCC1 or held LOW.

This guards against bus contentions and oscillations as

all inputs and the input VCC1 are powered at the same

time. The output VCC can then be powered to the target

voltage level to which the device will translate. The

output pin(s) then translate to logic levels dictated by the

output VCC levels.

Upon completion of these steps, the device can be

configured for the desired operation. Following these

steps helps prevent possible damage to the translator

device as well as other system components.

AC Loadings and Waveforms

Figure 3. AC Test Circuit

Figure 4. Waveform for Inverting and Non-Inverting Functions

Table 1.

AC Load Table

Symbol

VCC

3.3V ±0.3V

2.5V ±0.2V

1.8V ±0.15V

1.5V ±0.10V

1.2V ±0.10V

1.0V

Vmi

1.5V

VCC1/2

Vmo

1.5V

VCC/2

FXLP34 Scheda tecnica(PDF) 9 Page - ON Semiconductor