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REF3425MDBVTEP Scheda tecnica(PDF) 18 Page - Texas Instruments |
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REF3425MDBVTEP Scheda tecnica(HTML) 18 Page - Texas Instruments |
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18 / 28 page ![]() 1 6 2 3 4 GND_F GND_S EN OUT_F IN REF34xx-EP C 5 OUT_S 18 REF3425-EP, REF3430-EP, REF3433-EP, REF3440-EP SBAS942A – DECEMBER 2018 – REVISED MARCH 2019 www.ti.com Product Folder Links: REF3425-EP REF3430-EP REF3433-EP REF3440-EP Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated 12 Layout 12.1 Layout Guidelines Figure 22 illustrates an example of a PCB layout for a data acquisition system using the REF34xx-EP. Some key considerations are: • Connect low-ESR, 0.1-µF ceramic bypass capacitors at VIN, VREF of the REF34xx-EP. • Decouple other active devices in the system per the device specifications. • Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. • Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring. • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary. 12.2 Layout Example Figure 22. Layout Example |
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